A pixel sensor includes an array of pixel sensor cells that detects two dimensional signals. Pixel sensors include image sensors, which may convert a visual image to digital data that may be represented by a picture, i.e., an image frame. The pixel sensor cells are unit devices for the conversion of the two dimensional signals, which may be a visual image, into the digital data. A common type of pixel sensors includes image sensors employed in digital cameras and optical imaging devices. Such image sensors include charge-coupled devices (CCDs) or complementary metal oxide semiconductor (CMOS) image sensors.
While complementary metal oxide semiconductor (CMOS) image sensors have been more recently developed compared to the CCDs, CMOS image sensors provide an advantage of lower power consumption, smaller size, and faster data processing than CCDs as well as direct digital output that is not available in CCDs. Also, CMOS image sensors have lower manufacturing cost compared with the CCDs since many standard semiconductor manufacturing processes may be employed to manufacture CMOS image sensors. For these reasons, commercial employment of CMOS image sensors has been steadily increasing in recent years.
Referring to FIG. 1, an exemplary prior art semiconductor circuit comprising an image sensor pixel is shown. The exemplary prior art semiconductor circuit comprises a photosensitive diode PD, a global shutter transistor GS, a transfer gate transistor TG, a reset gate transistor RG, a source follower transistor SF, and a row select transistor RS. One end of the photosensitive diode PD is grounded, while the other end of the photosensitive diode PD is directly connected to the source of the global shutter transistor GS, which is herein referred to as a global shutter transistor source, and to the source of the transfer gate transistor TG, which is herein referred to as a transfer gate transistor source. The drain of the transfer gate transistor TG, which is herein referred to as a transfer gate transistor drain, constitutes a floating diffusion FD, which is electrically floating while the transfer gate transistor TG and the reset gate transistor are turned off. The floating diffusion FD is directly connected to the source of the reset gate transistor RG, which is herein referred to a reset gate transistor source, and to the gate of the source follower transistor SF, which is herein referred to the source follower transistor gate. While the floating diffusion FD is typically implemented as the drain of the transfer gate transistor TG, the floating diffusion FD may alternately implemented as the source of the reset gate transistor in a physical device.
The source of the source follower transistor SF is directly connected to the drain of the row select transistor RS, which is herein referred to as a row select transistor drain. The source of the row select transistor RS, which is herein referred to as a row select transistor source, is a “data out” node, or the node at which the output of the image sensor pixel. The drain of the reset gate transistor RG, the drain of the global shutter transistor GS, and the drain of the source follower are connected to a power supply voltage Vdd.
The exemplary prior art semiconductor circuit may be employed to form an array of image sensors to capture an image. Such an array of image sensors may be employed in any optical, infrared, or ultraviolet imaging device including digital cameras. Each image sensor unit is referred to as a pixel. The operation of the array of the image sensors includes an exposure sequence and a readout sequence. The exposure sequence may be performed simultaneously employing the global shutter method. The readout sequence is performed row by row, i.e., the time for performing the readout sequence varies from row to row. Thus, the hold time between the exposure sequence and the readout sequence varies from row to row.
During the exposure sequence, the amount of light impinging on the photosensitive diode PD is quantified by the amount of charge that accumulates in the floating drain node FD. All image sensor pixels in the entire array are exposed to photons that impinging thereupon at the same time for the same duration through the operation of a global shutter circuit. The photons are schematically represented by wavy arrows labeled “h.”
Initially, the global shutter control signal “gsc” turns on the global shutter transistor GS, which resets the photosensitive diode PD to a pinning voltage. The same global shutter control signal “gsc” is applied to all other global shutter transistors in an image sensor. The global shutter control signal “gsc” is then changed to turn off the global shutter transistor GS. At this step, the same global shutter control signal “gsc” is applied to all other global shutter transistors in the image sensor. All photosensitive diodes in the image sensor, including the photosensitive diode PD in FIG. 1, are exposed to impinging lights and generate charges. The electrical charges generated by the photosensitive diode PD continue to be accumulated on the node of the photosensitive diode PD tied to the global shutter transistor GS and the transfer gate transistor TG.
The reset gate RG is turned on by a reset gate control signal “rgc” so that the voltage level of the floating drain node FD is reset. The same reset gate control signal “rgc” is applied to all other reset gate transistors in the image sensor. Normally, the voltage at the floating drain node FD becomes substantially the same as the system power supply voltage Vdd. The reset gate RG is then turned on by a change in the reset gate control signal “rgc.” The same reset gate control signal “gsc” is applied to all other reset gate transistors to turn off all reset gate transistors in the image sensor. Since the floating drain node FD is floating, the voltage at the floating drain node FD remains at the same voltage before the reset gate transistor RG is turned off. The transfer gate TG is turned on by a transfer gate control signal “tgc,” which ends exposure of the photosensitive diode PD and integration of electrical charges in the photosensitive diode PD. The charged collected up to that point in the photosensitive diode is transferred through the transfer gate transistor TG to the floating drain node FD. The same transfer gate control signal “tgc” is applied to all other transfer gate transistors to transfer collected charges from each photosensitive diode to a corresponding floating drain node through a transfer gate transistor. The transfer gate transistor TG and all other transfer gate transistors in the image sensor are turned by a change in the transfer gate control signal “tgc.”
The readout sequence is performed row by row by selecting a row to be read out sequentially from the first row to the last row. The row select transistors in each row are controlled by a common row selection signal “rsc.” Thus, there may be as many independent common row selection signals as the number of rows. Once a row is selected, all row selection transistors RS in the selected row are turned on. The shift of the voltage at a floating drain node FD from the system power supply voltage Vdd is proportional to the amount of photons that the corresponding photosensitive diode PD generates, which is proportional to the amount of light impinging on the photosensitive diode PD. The voltage on the data out node of each pixel is read out in each column. The voltage level provides a first quantity related to the amount of electrical charge that the photosensitive diode PD generated.
The reset gate transistors are thereafter turned on for the selected row. This allows the readout of a second quantity, which is a background level signal for each pixel in the row. By subtracting the second quantity from the first quantity, any circuit related offset to the current measurement that generated the first quantity is compensated, i.e., any circuit specific contributions to the image data from the image sensor are eliminated.
However, there is a small amount of leakage of charge from the floating drain node FD to the substrate, through the transfer gate transistor TG, and the reset gate transistor RG since leakage current paths are present in almost every device. In practical terms, the most significant leakage is typically the leakage through the reset gate transistor. Such a leakage alters the voltage at the floating drain node FD during the hold time between the exposure sequence and the readout sequence. The greater the leakage, the greater the shift in the voltage during the hold time, and consequently, the greater the degree of image degradation from the array of the image sensor pixels.
The noise in the signal of an image sensor pixel increases with the hold time of the charge in the floating drain node FD. Thus, the noise due to leakage becomes a serious challenge in a global shutter method, which is employed in many CMOS image sensors to enable capture of images of high speed objects. The global shutter method employs a global shutter operation, in which the image for the whole frame is captured in the light conversion units of the pixels at the exact same time for all the rows and columns. The signal in each light conversion unit is then transferred to a corresponding floating diffusion. The voltage at the floating diffusions is read out of the imager array on a row-by-row basis. The global shutter method enables image capture of high speed subjects without image artifacts, but introduces a concern with the global shutter efficiency of the pixel since the integrity of the signal may be compromised by any charge leakage from the floating diffusion between the time of the image capture and the time of the reading of the imager array.
The image signal is held at the floating drain for varying amounts of time in the global shutter method. For example, the signal from the first row may have the least wait time which corresponds to the time needed to read out a single row, while the signal from the last row has the greatest wait time which almost corresponds to the full frame read-out time, during which the charge on the floating diffusion may be degraded due to charge leakage or charge generation. Any charge generations or charge leakage that occurs on the floating diffusion during the wait time can have a significant impact to the quality of the signal that is read out of the imager.
A metric of the efficiency in preserving the initial charge in the pixel is “global shutter efficiency,” which is the ratio of a signal that is actually read out of the pixel to the signal that would have been read out immediately after the signal was captured by the pixel. Ideally, the signal read out should be exactly the same as the signal captured, i.e., the global shutter efficiency should be 1.0 in an ideal CMOS image sensor. In practice, this is not the case due to the charge leakage and/or charge generation, and the picture quality is correspondingly degraded.
Since the floating diffusion of a transfer gate transistor typically consists of a p-n junction, any incident photons can generate additional charges on this node by photogeneration, which alters the charge signal being held at this node. The incident photons thus act as a source of noise for the signal held at the floating diffusion. In order to prevent the incident light from reaching the floating diffusion, current designs for an image sensor pixel employs interconnect level metal wiring formed above a via level as a light shield that blocks the incoming photons. The wiring of the metal interconnect level thus becomes restrictive to accommodate the light shield. Further, the light shield needs to be as close as possible to the floating diffusion in order to minimize the angles of incident photons that may be able to reach the floating diffusion from a glancing angle. In some cases, adding a light shield with accompanying changes to interconnect wiring structures may require increasing the wiring channels, which can adversely degrade the effective fill factor of the image sensor pixel used for light collection, or may add unnecessary capacitance to the floating diffusion.
In view of the above, there exists a need for a CMOS image sensor pixel structure that provides effective shielding of a floating diffusion without restrictions in metal wiring in metal interconnect levels, and a design structure for the same.
Further, there exists a need for a CMOS image sensor pixel structure that provides greater angular coverage of the floating drain without adversely affecting metal wiring in metal interconnect levels, and a design structure for the same.
Yet further, there exists a need for a CMOS image sensor pixel structure that does not require any increase in wiring channels while providing an effective blockage of light over the floating drain, and a design structure for the same.